This has been the case for at least a couple of decades.
All those devices don’t necessarily need the 3nm node - but all the engineering effort to make, say, a new mobile phone processor - will go towards a specific process node. Each process node your target for a new chip needs a set of masks for the photolithography process.
The smaller the process node, the more these masks end up costing (newer process nodes are approaching $50M per set). These masks are also custom made for the foundry you’re using them in (due to manufacturing variations), so if you want multiple foundries for security of supply, spend a few more tens of millions for each additional foundry.
The advantage of a small process node, though, is that the cost of the individual chips start to approach “free” once you’ve paid for that first one. :)
You can’t just make a new processor and run it on multiple process nodes without doing a whole lot of work, even besides mask sets. Any custom logic in the CPU core will have to be designed to work with that process node’s timing and power parameters. The timing closure on any process node is painstakingly detailed work - especially because you’d need a new mask set, or at least part of one.
Then you have to consider peripherals - when you build a processor, you’re going to need RAM. If you want to use the newest DDR5 on your processor, you need a DDR5 controller in your CPU to be able to talk to the memory. That DDR5 controller (provided and guaranteed by a third party, unless you want to try your hand at rolling your own) is only going to exist for one or two process nodes - again, because it’s a lot of work and expense to get up and running in the first place, so the vendor that provides that controller is only going to invest in the process nodes that make sense for it.
You’ll need these controllers for all your communication interfaces - USB, eMMC, PCIe, SPI, GPIO… And they all have to exist for the node you’ve chosen. Then you need to verify in simulation that your logic can interface to their logic at the speeds you want to run. It gets complicated really quickly.
This has been the case for at least a couple of decades.
All those devices don’t necessarily need the 3nm node - but all the engineering effort to make, say, a new mobile phone processor - will go towards a specific process node. Each process node your target for a new chip needs a set of masks for the photolithography process.
The smaller the process node, the more these masks end up costing (newer process nodes are approaching $50M per set). These masks are also custom made for the foundry you’re using them in (due to manufacturing variations), so if you want multiple foundries for security of supply, spend a few more tens of millions for each additional foundry.
The advantage of a small process node, though, is that the cost of the individual chips start to approach “free” once you’ve paid for that first one. :)
You can’t just make a new processor and run it on multiple process nodes without doing a whole lot of work, even besides mask sets. Any custom logic in the CPU core will have to be designed to work with that process node’s timing and power parameters. The timing closure on any process node is painstakingly detailed work - especially because you’d need a new mask set, or at least part of one.
Then you have to consider peripherals - when you build a processor, you’re going to need RAM. If you want to use the newest DDR5 on your processor, you need a DDR5 controller in your CPU to be able to talk to the memory. That DDR5 controller (provided and guaranteed by a third party, unless you want to try your hand at rolling your own) is only going to exist for one or two process nodes - again, because it’s a lot of work and expense to get up and running in the first place, so the vendor that provides that controller is only going to invest in the process nodes that make sense for it.
You’ll need these controllers for all your communication interfaces - USB, eMMC, PCIe, SPI, GPIO… And they all have to exist for the node you’ve chosen. Then you need to verify in simulation that your logic can interface to their logic at the speeds you want to run. It gets complicated really quickly.
Source: I’m a chip designer.
Edits: Fixing my terrible grammar.